Sponsors

Hosted by:
Technical University of Crete



Technical co-sponsor:
IEEE Computer Society

Xilinx

Altera

Maxeler Technologies

Data I/O Corporation

National Instruments


FPL Welcomes Sponsorships - for further information please contact

 

 

 



Program

Download "FPL 2011 Final Program" in pdf

September 5-7, Chania, Crete, Greece

FPL 2011 Program at a glance
Monday September 5th
8:00 – Conference Registration
9:00 – 9:10 Conference Opening
9:10 – 10:30 Keynote #1: Field Programmable Logic in investment banking – why scale and complexity drive the need for speed,
Dr. Stephen Weston, JP Morgan
10:30 – 11:00 Coffee Break & Poster Session 1
11:00 – 12:30 M1.1 Scientific Applications M1.2 Modeling and Generators M1.3 NoCs on FPGA
12:30 – 14:00 LUNCH
14:00 – 15:30 M2.1 Embedded Reconfigurable Systems M2.2 Reconfigurable Architectures M2.3 Computation and Identity
15:30 – 16:00 Coffee Break & Poster Session 2
16:00 – 17:30 M3.1 Packet Processing M3.2 Signal and Image Processing M3.3 FPGAs and Processor Architecture
19:30 – 21:00 Welcome Reception and Demo Night
Tuesday September 6th
8:00 – Conference Registration
9:10 – 10:30 Keynote #2:Reconfigurable Systems Emerge 2.0,
Nick Tredennick
10:30 – 11:00 Coffee Break & Poster Session 3
11:00 – 12:30 T1.1 HPC Reconfigurable Systems T1.2 Device Aging and Tools
12:30 – 14:00 LUNCH
14:00 – 15:30 T2.1 Tools and Open-Source T2.2 Filtering and Stream Processing
15:30 – 16:00 Coffee Break & PhD Forum
16:00 – 17:30 T3.1 Search Strategies T3.2 Back-end Tools T3.3 FPGA Architecture & Interconnect
20:00 Transport to Gala dinner
21:00 Gala dinner
Wednesday September 7th
9:00 – Conference Registration
9:30 – 10:15 Coffee Break & Poster Session 4
10:15 – 11:45 W1.1 Cryptographic Applications W1.2 Floorplanning and Debug W1.3 FPGA Timing and Applications
11:45 – 12:00 Conference Closing Remarks
12:00 – 13:00 LUNCH

 


FPL 2011 Program

Monday September 5th

[8:00] Conference Registration
[9:00 – 9:10] Conference Opening

[9:10 – 10:30] Keynote #1:Field Programmable Logic in investment banking – why scale and complexity drive the need for speed,
Dr. Stephen Weston, JP Morgan

[10:30 – 11:00] Coffee Break and Poster Session 1
Accelerating Image Analysis for Localization Microscopy with FPGAs
Frederik Grüll, Manfred Kirchgessner, Rainer Kaufmann, Michael Hausmann and Udo Kebschull
Unifying option-pricing designs for hardware acceleration
Qiwei Jin, David Thomas and Wayne Luk
Leros: A Tiny Microcontroller for FPGAs
Martin Schoeberl
Design of a High Switching Frequency FPGA-Based SPWM Generator for DC/AC Inverters
Matina Lakka, Eftichios Koutroulis and Apostolos Dollas
A New Process Characterization Method for FPGAs based on Electromagnetic Analysis
Florent Bruguier, Pascal Benoit, Philippe Maurine and Lionel Torres
An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors
Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb, Vikram Bhatt, Steve Swanson and Michael Bedford Taylor
Multi-Module Hashing System for SHA-3 & FPGA Integration
Nicolas Sklavos
A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAS
Harry Sidiropoulos, Kostas Siozios and Dimitrios Soudris
Dependable optically reconfigurable gate array with a phase-modulation type holographic memory
Takahiro Watanabe and Minoru Watanabe
[11:00 – 12:30] Monday Morning Session
M1.1 Scientific Applications
Session Chair: Joao Cardoso, University of Porto
[11:00 - 11:30] An FPGA Solver for SAT-encoded Formal Verification Problems,
Kenji Kanazawa and Tsutomu Maruyama
[11:30 – 12:00] FPGA-Based Prototyping of Generalized Laguerre-Volterra MIMO Model for Neural Science Research
Will X. Y. Li, Rosa H. M. Chan, Wei Zhang, Ray C. C. Cheung, Dong Song and Theodore W. Berger
[12:00 – 12:30] Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms
Jason Cong, Muhuan Huang and Yi Zou
M1.2 Modeling and Generators
Session Chair: Dirk Koch, University of Oslo
[11:00 - 11:30] Latch-Based Performance Optimization for FPGAS
Bill Teng and Jason H. Anderson
[11:30 – 12:00] XDL-Based Module Generators for Rapid FPGA Design Implementation
Subhrashankha Ghosh and Brent Nelson
[12:00 – 12:30] Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-based Systems using Stochastic Networks
Rehan Ahmed and Peter Hallschmid
M1.3 NoCs on FPGA
Session Chair: Daniel Ziener, University of Erlangen-Nuremberg
[11:00 - 11:30] A Radix Tree Router for Scalable FPGA Networks
William V. Kritikos, Yamuna Rajasekhar, Andrew G. Schmidt and Ron Sass
[11:30 – 12:00] Generic Low-Latency NoC Router Architecture for FPGA Computing Systems
Ye Lu, John McCanny and Sakir Sezer
[12:00 – 12:30] Scalable arbiters and multiplexers for on-FGPA interconnection networks
Giorgos Dimitrakopoulos, Christoforos Kachris and Emmanouil Kalligeros
[12:30 – 14:00] LUNCH
[14:00 – 15:30] Monday Afternoon Session
M2.1 Embedded Reconfigurable Systems
Session Chair: Fearghal Morgan, NUI Galway
[14:00 – 14:30] 20Gbps C-Based Complex Event Processing
Hiroaki Inoue, Takashi Takenaka and Masato Motomura
[14:30 – 15:00] Embedded Systems Start-up under Timing Constraints on Modern FPGAs
Joachim Meyer, Juanjo Noguera, Michael Huebner, Rodney Stewart and Juergen Becker
[15:00 – 15:30] Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method
Yuan Li, Paul Chow, Jiang Jiang and Minxuan Zhang
M2.2 Reconfigurable Architectures
Session Chair: Cristina Silvano, Politecnico di Milano
[14:00 – 14:30] A Run-Time Adaptive FPGA Architecture for Monte Carlo Simulations
Xiang Tian and Christos-Savvas Bouganis
[14:30 – 15:00] PRECORE – A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation
Benjamin Thielmann, Jens Huthmann and Andreas Koch
[15:00 – 15:30] Implementing stream-processing applications on FPGAs : a DSL-based approach
Jocelyn SEROT, Francois BERRY and Sameer AHMED
M2.3 Computation and Identity((Stamatis Vassiliadis Award Candidates‡)
Session Chair: Christos Bouganis, Imperial College
[14:00 – 14:30] Revisiting the Newton-Raphson Iterative Method for Decimal Division
Horácio Neto and Mário Véstias
[14:30 – 15:00] Hardware Support for Broadcast and Reduce In Mpsoc
Yuanxi Peng, Manuel Saldaña and Paul Chow
[15:00 – 15:30] The Impact of Aging on An FPGA-Based Physical Unclonable Function
Abhranil Maiti, Logan McDougall and Patrick Schaumont
[15:30 – 16:00] Coffee Break and Poster Session 2
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operaters
Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi and Shinobu Nagayama
Multi-Module Hashing System for SHA-3 & FPGA Integration
Nicolas Sklavos
FPGA-Accelerated Object Detection Using Edge Information
Christos Kyrkou, Christos Ttofis and Theocharis Theocharides
Memory-efficient and fast run-time reconfiguration of regularly structured designs
Brahim Al Farisi, Karel Heyse, Karel Bruneel and Dirk Stroobandt
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware
Juan Clemente, Ivan Beretta, Vincenzo Rana, David Atienza and Donatella Sciuto
RAMPSOCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive Mpsoc
Diana Goehringer, Stephan Werner, Michael Huebner and Juergen Becker
Memory Virtualization for Multithreaded Reconfigurable Hardware
Andreas Agne, Enno Lübbers and Marco Platzner
Implications of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures
Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto and Takao Onoye
ERDB: An Embedded Routing Database for reconfigurable systems
Krzysztof Kepa, Fearghal Morgan and Peter Athanas
[16:00 – 17:30] Monday Evening Session
M3.1 Packet Processing
Session Chair: Eduardo de la Torre, Universidad Politécnica de Madrid
[16:00 – 16:30] Clustered Parameterized Hierarchical Search Structure for Large-Scale Packet Classification on FPGA
Oğuzhan Erdem, Hoang Le and Viktor Prasanna
[16:30 – 17:00] Thwarting Software Attacks on Data-intensive Platforms with Configurable Hardware-assisted Application Rule Enforcement
Mohammed Farag, Lee Lerner and Cameron Patterson
[17:00 – 17:30] Towards on-the-fly Incremental Updates for Virtualized Routers on FPGA
Thilan Ganegedara, Hoang Le and Viktor Prasanna
M3.2 Signal and Image Processing
Session Chair: Marco Santambrogio, Politecnico di Milano
[16:00 – 16:30] An Implementation of the Mean Shift Filter on FPGA (Stamatis Vassiliadis Award Candidate)
Dang Ba Khac Trieu and Tsutomu Maruyama
[16:30 – 17:00] Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs
Hadi P. Afshar and Paolo Ienne
[17:00 – 17:30] FPGA-Specific Arithmetic Optimizations of Short-Latency Adders
Hong Diep Nguyen, Bogdan Pasca and Thomas B. Preußer
M3.3 FPGAs and Processor Architecture
Session Chair: Jason Anderson, University of Toronto
[16:00 – 16:30] A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAS
Harry Sidiropoulos, Kostas Siozios and Dimitrios Soudris
[16:30 – 17:00] FlexCache: Field Extensible Cache Controller Architecture Using On-Chip Reconfigurable Fabric
Daniel Lo, Greg Malysa and G. Edward Suh
[17:00 – 17:30] VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic
Lei Yuanwu, Dou Yong, Zhou Jie and Sufeng Wang
[19:30 – 21:00] Welcome Reception and Demo Night

Tuesday September 6th, Morning

[8:00] Conference Registration

[9:10 – 10:30] Keynote #2, Reconfigurable Systems Emerge 2.0,
Nick Tredennick

[10:30 – 11:00] Coffee Break and Poster Session 3
A Dynamically-Reconfigurable Phased Array Radar Processing System
Emmanuel Seguin, Russell Tessier, Eric Knapp and Robert Jackson
Exploitation of Parallel Search Space Evaluation with FPGAs in Combinatorial Problems: The Eternity II Case
Pavlos Malakonakis and Apostolos Dollas
A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware
Abdulkadir Akin, Onur Can Ulusel, Tevfik Zafer Ozcan, Gokhan Sayilar and Ilker Hamzaoglu
A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values
Mark Hamilton, William P. Marnane and Arnaud Tisserand
Stress-Aware Module Placement on Reconfigurable Devices
J. Angermeier, D. Ziener, M. Glass and J. Teich
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong and Lei He
A Routing Architecture for Mapping Dataflow Graphs at Run-time
Dirk Koch and Jim Torresen
An Easily Testable Routing Architecture And Efficient Test Technique
Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi
Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs
Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Raul Torrego and Imanol Martinez
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs
Vasco Bexiga, Carlos Leong, Jorge Semião, Maria Dolores Valdès, Judit Freijedo, Juan Rodriguez-Andina, Fabian Vargas, Isabel C. Teixeira and J. Paulo Teixeira
[11:00 – 12:30] Morning Session
T1.1 HPC Reconfigurable Systems
Session Chair: Russell Tessier, University of Massachusetts
[11:00 – 11:30] A Model for Matrix Multiplication Performance on FPGAs
Colin Y. Lin, Hayden K.-H. So and Philip H.W. Leong
[11:30 – 12:00] Exploring Gabor Filter Implementations for Visual Cortex Modeling
Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick and Vijaykrishnan Narayanan
[12:00 – 12:30] High Frequency Trading Acceleration using FPGAs
Christian Leber, Benjamin Geib and Heiner Litz
T1.2 Device Aging and Tools (Michal Servit Award Candidates†)
Session Chair: Brent Nelson, Brigham Young University
[11:00 – 11:30] Improving FPGA reliability using wear-leveling
Edward Stott and Peter Y.K. Cheung
[11:30 – 12:00] A Low-Cost Sensor for Aging and Late Transitions Detection In Modern FPGAs
Abdulazim Amouri and Mehdi Tahoori
[12:00 – 12:30] Reducing FPGA Router Run-time Through Algorithm and Architecture
Marcel Gort and Jason Anderson
[12:30 – 14:00] LUNCH
[14:00-15:30] Tuesday Afternoon Session
T2.1 Tools and Open-Source (Community Service Award Candidates ◊)
Session Chair: Wayne Luk, Imperial College
[14:00 – 14:30] Fast RTL Power Estimation for FPGA Designs
Paul Schumacher, Pradip Jha, Sudha Kuntur, Tim Burke and Alan Frost
[14:30 – 15:00] RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs
Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent Nelson and Brad Hutchings
[15:00 – 15:30] Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
Michel Kinsy and Michael Pellauer
T2.2 Filtering and Stream Processing
Session Chair: Jack Sampson, UCSD
[14:00 – 14:30] Separable Fir Filtering In FPGA and GPU Implementations: Energy, Performance, and Precision Considerations
Daniel Llamocca, Cesar Carranza and Marios Pattichis
[14:30 – 15:00] Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs
Andrés Otero, Teresa Cervero, Eduardo De la Torre, Sebastián López, Gustavo Callicó, Teresa Riesgo and Roberto Sarmiento
[15:00 – 15:30] Compact Hardware Architecture for Hummingbird Cryptographic Algorithm
İsmail San and Nuray At
[15:30 – 16:00] Coffee Break and Ph.D. Forum
Pipelined Floating-Point Architecture for a Phase and Magnitude Detector based on CORDIC
Pongyupinpanich Surapong and Manfred Glesner
Failure Probability and Fault Observability of SRAM-FPGA Systems
Cinzia Bernardeschi, Luca Cassano and Andrea Domenici
FPGA-based acceleration of Block Matching Motion Estimation
Diego González Rodríguez, Guillermo Botella Juan, Soumak Mookherje and Uwe Meyer-Bäse
An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives Control
Bogdan Alecsa and Alexandru Onea
Mechanisms and architecture for the dynamic reconfiguration of an advanced wireless sensor node
François Philipp and Manfred Glesner
Real-Time Evaluation of Remote Sensing Data on Board of Satellites
Kurt Schwenk, Felix Huber, Katharina Goetz and Maria von Schoenermark
Heterogeneous Platform for Stream Based Applications on FPGAs
Jan Kloub, Tomas Mazanec and Antonin Hermanek
[16:00 – 17:30] Evening Session
T3.1 Search Strategies
Session Chair: Eftichios Koutroulis, Technical University of Crete
[16:00 – 16:30] Implementation in FPGA of Address-Based Data Sorting
Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov and Alexander Sudnitson
[16:30 – 17:00] Novel and highly efficient reconfigurable implementation of Data Mining Classification Tree
Grigorios Chrysos, Panagiotis Dagritzikos, Ioannis Papaefstathiou and Apostolos Dollas
[17:00 – 17:30] FPGA Acceleration of the Phylogenetic Parsimony Kernel
Nikolaos Alachiotis and Alexandros Stamatakis
T3.2 Back-end Tools
Session Chair: Dirk Stroobandt, Ghent University
[16:00 – 16:30] Timing-Driven Routing of High Fanout Nets
Xun Chen, Jianwen Zhu and Minxuan Zhang
[16:30 – 17:00] Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs
Stefan Wildermann, Jürgen Teich and Daniel Ziener
[17:00 – 17:30] Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign
Seong-I Lei and Wai-Kei Mak
T3.3 FPGA Architecture & Interconnect
Session Chair: Michael Hübner, Karlsruhe Institute of Technology
[16:00 – 16:30] A Radiation Hard LUT Block with Auto-Scrubbing
Kashfia Haque and Paul Beckett
[16:30 – 17:00] FPGA Interconnect Architecture Exploration Based on a Statistical Model
Zhen Wang, Ding Xie and Jinmei Lai
[17:00 – 17:30] Capacitive Boosting for FPGA Interconnection Networks
Fatemeh Eslami and Mihai Sima
[20:00] Transport to Gala Dinner location
[21:00] Gala Dinner

Wednesday September 7th

[9:00] Conference Registration
[9:30 – 10:15] Coffee Break and Poster Session 4
Scalable FRM-SSA SOC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time
Orsalia Georgia Hasapis and Elias Manolakos
SYNTHESIZING TILED MATRIX DECOMPOSITION ON FPGAS
Yi-Gang Tai, Chia-Tien Dan Lo and Kleanthis Psarris
Acceleration of Multi-agent Simulation on FPGAs
Lintao Cui, Jing Chen, Bryan Hu and Jinjun Xiong
Molecular Docking on FPGA and GPU Platforms
Imre Pechan and Béla Fehér
Pattern compression of FAST corner detection for efficient hardware implementation
Keisuke Dohi, Yuji Yorita, Yuichiro Shibata and Kiyoshi Oguri
IPF: In-Place X-Filling to Migrate Soft Errors in SRAM-Based FPGAS
Zhe Feng, Naifeng Jing and Lei He
Resource Management for the Heterogeneous Arrays of Hardware Accelerators
Zdenek Pohl and Milan Tichy
A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine
Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada and Tsutomu Yoshinaga
Remote FPGA Lab with Interactive Control and Visualisation Interface
Fearghal Morgan, Seamus Cawley, Frank Callaly, Shane Agnew, Patrick Rocke, Martin O'Halloran and Nina Drozd
[10:15 – 11:45] Wednesday Morning Session
W1.1 Cryptographic Applications
Session Chair: Ron Sass, University of North Carolina at Charlotte
[10:15 – 10:45] Cryptographic extension for soft general-purpose processors with secure key management
Lubos Gaspar, Viktor Fischer, Lilian Bossuet and Milos Drutarovsky
[10:45 – 11:15] Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs
Rajesh Velegalati and Jens-Peter Kaps
[11:15 – 11:45] Compact CLEFIA Implementation on FPGAs
Ricardo Chaves and Paulo Proenca
W1.2 Floorplanning and Debug
Session Chair: Dimitrios Soudris, National Technical University of Athens
[10:15 – 10:45] Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
Yousef Iskander, Stephen Craven and Cameron Patterson
[10:45 – 11:15] Speculative Debug Insertion for FPGAs
Eddie Hung and Steven J. E. Wilton
[11:15 – 11:45] Automated Resource-aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems
Cristiana Bolchini, Antonio Miele and Chiara Sandionigi
W1.3 FPGA Timing and Applications
Session Chair: Fabrizio Ferrandi, Politecnico di Milano
[10:15 – 10:45] On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry
Haile Yu, Qiang Xu and Philip H. W. Leong
[10:45 – 11:15] Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking
Xin Yu Niu, Kuen Hung Tsoi and Wayne Luk
[11:15 – 11:45] Optimizing an Open-Source Processor for FPGAs: A Case Study
Lyonel Barthe, Luís Vitório Cargnini, Pascal Benoit and Lionel Torres
[11:45 – 12:00] Conference Closing
[12:00 – 13:00] LUNCH