Sponsors

Hosted by:
Technical University of Crete



Technical co-sponsor:
IEEE Computer Society

Xilinx

Altera

Maxeler Technologies

Data I/O Corporation

National Instruments


FPL Welcomes Sponsorships - for further information please contact

 

 

 



Workshops & Tutorials

List of Workshops

 


"Computer Vision on Low-Power Reconfigurable Architectures"

Date: Sunday September 4, 2011
Time: 1pm to 6pm
Program: Computer Vision Program
Location: Porto Platanias Hotel
Chair: Dr. Markus Koester, University of Paderborn, Germany

Scope and Topics

In the past decade the field of computer vision has grown significantly in research, development and applications. Computer vision is used in various domains ranging from object recognition, robotics, and scene reconstruction to automation and interaction. The general superiority of visual information in diversity and reliability over other sensors' is more apparent than ever. As sensor technology continues to improve, image resolutions increase at growing frame rates. In order to achieve real-time video processing, suitable processing platforms are required which provide the required processing performance while keeping power consumption low. Today's pursuit of highly capable and long lasting battery-powered mobile systems and devices puts tight constraints on energy consumption and device size. Research in computer vision as well as video and image processing has mainly focused on elevating the functionalities while little attention has been paid to power-aware computation. For the application of cutting-edge computer vision methods in real world systems and industrial applications it is essential to migrate from powerful workstations towards embedded processors and enforce the associated shift in application development and implementation. The objective of this workshop is to examine the state of the art in the application of reconfigurable devices in computer vision applications. In particular the potential of low-power, energy-efficient FPGAs, GPGPUs and many-cores in the context of computer vision applications is of interest. We aim to bring together the leading researchers and developers from academia and industry in order to facilitate the exchange of ideas and experiences from research and real-world applications and to discuss future directions.
Call for Papers and more details...

 

"Xilinx Workshop - Embedded System Design using AXI"

Date: September 8 - 9, 2011
Time: for both days

  • Start time - 9:00 AM
  • Morning break - 10:30 AM
  • Lunch break - 12:30 PM
  • Afternoon break - 3:15 PM
  • End time - 5:00 PM

Location: Porto Platanias Hotel
Instructor: Dr. Parimal Patel

Online Registration (Max No. of participants: )

Scope and Topics

Xilinx University Program (XUP) is pleased to offer a two days workshop on Embedded System Design flow in Xilinx FPGA using Xilinx Embedded Development Kit (EDK) tools. After attending this workshop, you will be able to rapidly architect an embedded system targeting a hardware platform, create a custom peripheral, and develop an interrupt service routine. This workshop will cover embedded systems design using AXI4 interface. For details, please visit:
http://www.xilinx.com/university/workshops/embedded-system-design-flow/index.htm.

 

"Altera Workshop - Teaching Digital Logic and Embedded Systems with Altera's FPGAs, Tools and Boards."

Date: September 4, 2011
Time:

  • Start time - 9:30 AM
  • Morning break - 10:45 AM
  • Lunch break - 12:00 PM
  • Afternoon break - 2 PM
  • End time - 4:00 PM

Location: Porto Platanias Hotel
Instructor: Dr. Tom Czajkowski

Registration: To register for the course, please email at
(Max No. of participants: 20)

Scope and Topics

This course begins with an short introduction to Altera and the FPGA technology, followed by two practical sections in which participants get hands-on instruction on how to use Quartus II and other Altera tools. The first section deals with basic digital logic design, where we show how to use Quartus II to design simple logic circuits and program them onto the Altera DE1 boards (provided for the purposes of the course). We then show a few tools, such as the RTL Viewer/SignalTap II, to demonstrate how they can be used to help students debug their circuits.

The second section discusses the topic of embedded systems and present tools for building systems on a programmable chip. We will show how to work with these tools and how they can be used for teaching university-level embedded systems courses.

Throughout the workshop, I will also present teaching materials we provide that relevant to each section. These include laboratory exercises that demonstrate the key concepts in the courses we discuss, as well as tutorials that explain how to use our tools. Both are written for university-level students, allowing the students to easily follow the explanations on their own without difficulty.

 

"Azido - A System-Level Design Tool to Exponentially Improve Application Productivity for FPGA"

Date: Thursday, September 8th, 2011
Time: 9am to 1pm
Location: Porto Platanias Hotel
Tutorial Format: A powerpoint presentation, product demonstration and interactive group exercise.
Presenter: Mr. Kent Gilson
Kent Gilson is an experienced entrepreneur and innovator with over 20 years leading research and development teams in the areas of reconfigurable computing, EDA tools, and HPC applications. As one of the early developers of reconfigurable computing he wrote the first patent on embedding soft processors in FPGAs.

For questions and to register for the workshop, please email to

Scope and Topics

Azido is a system-level, graphical, object-oriented, parallel programming design tool that exponentially improves application productivity for FPGA designs. Azido changes current FPGA application development from an ASIC design flow to software programming. Its environment easily facilitates IP reuse and system retargeting while providing much faster system-level design iteration and debug capabilities. Azido is unique in many ways. It is mathematically based, starting with first engineering principles. Therefore, all design work is inherently mathematically tested and verified. It includes recursion, transports, data scatter/gather, data flow and a multitude of memory subsystems enabling a full system-level design environment. It also separates "the design" from "the architectural implementation", so retargeting a design into a different IC or system is as simple as saying so.

 

"National Instruments Workshop - A Graphical FPGA Development Environment for Application Domain Experts."

Date: Sunday, September 4th, 2011

NEW DATE AND TIME:
Wednesday, Sept. 7, 14:30 - 19:00

Time: 1pm to 5pm
Location: Porto Platanias Hotel
Expected tutorial format: Demo/hands-on 6 stations (LabVIEW laptop/RIO board)
Organizers/presenters, affiliations, and short bios:
Hugo Andrade, National Instruments Corp., USA
Mr. Hugo Andrade is a Principal Architect in the LabVIEW Platform Group at National Instruments. Mr. Andrade earned his BS and MS degrees from the University of Texas at Austin. He has led standardization efforts on instrument control software and the early R&D of LabVIEW FPGA. He currently manages the NI Berkeley R&D site. He holds 40 patents in the areas of instrumentation software, hw/sw interfacing, reconfigurable computing, graphical programming, and system-level design.
Guoqiang Wang, National Instruments Corp., USA
Dr. Guoqiang Wang is a Staff R&D Software Engineer in the LabVIEW Platform Group at National Instruments’ Berkeley R&D office. His research interests include early high-level timing analysis for FPGA design, timed model of computation, distributed real-time embedded systems, model-based and system-level design methodologies, etc. He holds a Ph.D. degree from University of California, Berkeley.
Dustyn Blasig, National Instruments Corp., USA
Mr. Dustyn Blasig is a Senior Computer Engineer in the LabVIEW Platform R&D Group at National Instruments in Austin, TX. He is an active contributor to the development of the LabVIEW Platform and the LabVIEW FPGA Module. His current focus is on the advancement of the LabVIEW FPGA compiler. He acquired his BS and MS degrees from the University of Texas at Austin.

For questions and to register for the workshop, please email to

Scope and Topics

In this tutorial we present a graphical programming environment for hardware designs targeted at FPGA devices. FPGAs have become very popular for implementing embedded systems such as controllers for industrial machinery, medical equipment, vehicles, or other electromechanical devices, etc. However, most of the application domain experts designing or prototyping these kinds of systems are not familiar with hardware programming. In this tutorial, we present how LabVIEWTM, a scientific software system, enables domain experts to leverage the benefits from reconfigurable hardware for implementation and deployment. We first introduce the design environment and its modular virtual instrumentation programming paradigm. Then, we discuss how LabVIEW FPGA enables application domain experts without prior knowledge of hardware description languages (HDLs) to program reconfigurable hardware devices for motion control, custom digital communication, and system timing and synchronization applications.

You will gain hands-on experience with LabVIEW and the RIO (Reconfigurable I/O) hardware platform, based on a tightly coupled real-time processor, an FPGA, and configurable modular front-end analog and digital I/O. We will present details on the environment’s modeling, simulation, and debugging capabilities as well as its rigorous semantics as a programming and deployment framework. Furthermore, we use application use cases to illustrate how LabVIEW FPGA can support a flexible, reliable and cost-effective hardware design. We will explore leading-edge control design tools and techniques to improve your design efficiency by using the NI Robotics Kit and Single Board RIO hardware platforms. We end with a discussion on how LabVIEW facilitates reconfigurable hardware designs for applications of ultra-high speed control and communications, complex timing and synchronization, hardware-in-the-loop (HIL) testing, etc.


"European Union Projects Workshop"

Date: Wednesday September 7, 2011
Time: 2:30pm-7:30pm
Location: Porto Platanias Hotel
Organized by: Prof. João Cardoso (U. Porto), Prof. Christina Silvano (Politecnico di Milano)
Programme: EU Funded Projects Workshop Program

Scope and Topics

This workshop is mainly organized around five EU funded FP7 projects, namely 2PARMA (PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures, http://www.2parma.eu/), MADNESS (Methods for predictAble Design of heterogeNeous Embedded System with adaptivity and reliability Support, http://www.madnessproject.org), REFLECT (Rendering FPGAs to Multi-Core Embedded Computing, http://www.reflect-project.eu/), SMART (Secure, Mobile visual sensor networks ARchiTecture, http://www.artemis-smart.eu/ ) and HEAP (A Highly Efficient Adaptive multi-Processor Framework, http://www.fp7-heap.eu/ ). This workshop will present the approaches and research efforts being explored, the results achieved, and the proposed research avenues of these three projects. The workshop will include a panel discussion for exchange of ideas, information, and opinions regarding research opportunities in embedded computing systems in Europe.